Satish Puri

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Research Interests : Parallel and Distributed Computing, Spatial Big Data, and High Performance Computing.

Email: satish.puri (at) marquette (dot) edu

Assistant Professor
Department of Computer Science
Marquette University

Brief Bio

PhD, Computer Science, Georgia State University, Atlanta, August 2015
Bachelor of Technology (B.Tech), Computer Science and Engineering, National Institute of Technology (NIT), India, 2008

Spring 2023 Semester Classes

COSC 6600, Parallel and Distributed Systems, Syllabus Link

COSC 3100, Algorithms

Office Hours

Monday: 2 pm to 4 pm
Wednesday: 3 pm to 4 pm

New Publications

Efficient PRAM and Practical GPU Algorithms for Large Polygon Clipping with Degenerate Cases, 23rd IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGrid), May 2023. Acceptance rate 21%, Best Papers Finalist. Paper

Fine-grained Dynamic Load Balancing in Spatial Join by Work Stealing on Distributed Memory, November, ACM SIGSPATIAL 2022, Seattle, WA. Paper, Github Code

Accelerating Spatial Autocorrelation Computation with Parallelization, Vectorization and Memory Access Optimization, 22nd IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGrid), Italy, May 2022 (Paper, IEEE Link), Acceptance Rate 24% (75/302 submissions)

Teaching SIMD Instructions using Intel Intrinsics in Computer Organization Course, Lightning Talks of EduHPC 2021.
EduHPC-21 Workshop, EduHPC@SC 2021, November, 2021 Paper, Slides and Code on GitHub, Video

Efficient Filters for Geometric Intersection Computations using GPU, ACM SIGSpatial, 2020. Paper, Github Code, Slides, Video

Efficient Parallel and Adaptive Partitioning for Load-balancing in Spatial Join, IEEE IPDPS 2020. Paper link, Video, Slides

Hierarchical Filter and Refinement System over Large Polygonal Datasets on CPU-GPU, IEEE HiPC, 2019. Paper, Github Code, Slides

Current Research

The new research will revisit spatial data analytics on heterogeneous systems comprised of data processing units (DPU). These DPUs are a new class of programmable processors made by NVidia (and other manufacturers). Similar to a modern smart network interface card, DPUs can be used to filter unnecessary data from overwhelming the CPU and memory bandwidth. DPUs can be used by CPUs to offload computations; thereby reducing the load on CPU and increasing the capability of the compute node.

The next research thrust is to design communication-efficient spatial analytics algorithms on high performance computing (HPC) systems.

In the past, our lab has worked on the following topics:

Parallelization of Computational Geometry Algorithms on Multi-cores and GPUs.

MPI-GIS: A Message Passing Interface based system for large-scale geospatial data (GitHub Code)

Parallel I/O and Partitioning for irregular variable-length data on parallel filesystems

New Opening for a PhD Student starting from Fall 2023.
For prospective PhD students, here is the link to apply: Apply to our CS PhD program.


Review Board Member, IEEE Transactions on Parallel and Distributed Systems (TPDS), 2020 and 2021.
Reviewer, Journal of Parallel and Distributed Computing (JPDC), 2019, 2020, 2021
Program Committee Member, IEEE International Conference on High Performance Computing, Data and Analytics, 2021
Program Committee Member, IEEE/ACM International Symposium on Cluster, Cloud and Internet Computing (CCGrid 2020).
Program Committee Member, International Conference on Parallel Processing (ICPP), 2019.
NSF Panelist, 2018, 2019, 2020, 2021
Workshop Proceedings Chair, EduHPC, EduPar 2019,2018,2017,2016.

Primary links